The present invention relates to transistors, and more particularly to the fabrication of electrostatic discharge transistors in Flash memory arrays.
Flash memory chips are conveniently packaged as xe2x80x9cflash cards,xe2x80x9d using PC Card, CompactFlash, Smart Media and similar formats. Flash memory has become widely used as film in digital cameras as well as auxiliary storage in a variety of handheld commercial and consumer devices. A flash memory chip typically includes a core area and a periphery area. The core area comprises an array of memory transistors for storing data, where each column of memory transistors is accessed by a select transistor. The transistors in the core area have a stacked gate structure, which includes a floating gate comprising a type-1 layer of polysilicon (poly 1) underneath a control gate, which comprises a type-2 layer of polysilicon (poly 2). The layer of poly 2 also forms word lines and select lines in the flash memory array. The transistors in the core area are referred to as poly 1 transistors.
The periphery area of the flash memory chip includes switching logic for the chip. Because flash memory cards are constantly inserted and removed from electronic devices, the periphery area of flash memory chips are provided with protective circuits that prevent damage due to electrostatic discharge (ESD). ESD circuits are normally placed between input/output pads and transistor gates to which the pads are connected. One type of protective circuit is referred to as an ESD transistor. The transistors in the periphery area, including the ESD transistors, have only one gate comprising a layer of poly 2. Thus, these transistors are referred to as poly 2 transistors.
An ESD transistor in the periphery area comprises a gate, source and drain, but the drain is formed by two implants. FIG. 1 is a flow chart illustrating the processing steps involved in the formation of a conventional ESD transistor in the periphery area of a flash memory. Also shown is a series of cross-sectional views of a substrate showing the resulting structure.
The process begins by depositing a layer of poly 2 on a substrate 50 in step 10. This is followed by a poly 2 mask and etch in steps 12 and 14, resulting in a poly 2 gate. After formation of the gate, a LDD mask and LDD implant are performed in steps 16 and 18 to form lightly doped drains (LDD""s) 52 at the edge of the channel.
Next, an ESD implant mask and ESD implant are performed in steps 20 and 22 to form a hard MDD (medium doped drains) junction 54. This heavier second implant typically comprises arsenic at a dose of approximately 1xc3x971014 to 2xc3x971015 atoms/cm2.
After formation of the hard junction 54, a layer of oxide 56 is deposited step 24. The oxide 56 is then etched to form LDD side-wall spacers 57 adjacent to the gate in step 26. After the LDD spacers are 57 formed, a N+ implant mask is performed in step 28 followed by a N+ implant in steps 30 to form N+ source and drain regions 58.
Although conventional ESD transistors adequately protect integrated circuits from electrostatic discharge, they have the disadvantage of requiring an extra ESD implant mask, which adds fabrication steps and increases cost.
Accordingly, what is needed is a transistor structure for protecting against electrostatic discharge that does not require an extra ESD implant mask. The present addresses such a need.
The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.
According to the method and apparatus disclosed herein, the present invention provides an ESD transistor based on a poly 1 select gate transistor, rather than a poly 2 transistor. During memory array fabrication when poly 1 select gate transistors are formed, poly 1 select gate transistors are also located in the memory array where ESD protection is desired. Thereafter, these poly 1 select gate transistors are transformed into ESD transistors, but in less processing steps than required for convention poly 2 ESD transistors.